Their loading logic require a lot of cells and seem complex, but in the end it forms something quite simple. The parallel-in-serial-out shift registers used for the serial link and video rendering are made of chains of set-reset-capable DFFs. Some DFF clock polarities have to be verified. Others might be state indicators like the Z80 /M1 or HALT. Many of them are trigger and acknowledge signals for interrupts. Nets named FROM_CPU* and TO_CPU are connected to the CPU core but are not clearly identified.
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